1. Field of the Invention
The present invention relates to a layout design method which creates a multi-layered semiconductor integrated circuit through a cell layout technique, and relates to a semiconductor integrated circuit which is created by the layout design method.
2. Description of the Related Art
In the layout design of semiconductor integrated circuits, a layout creation tool which is called the automatic placement/wiring tool is used. In the layout creation tool, the structure information of basic cells, such as inverters and NANDs, are registered in the database in advance, the structure information of a desired cell is read from the database and arranged in a predetermined region of a chip layout, so that a semiconductor integrated circuit which meets the given specifications is acquired.
FIG. 1 is a flowchart for explaining a conventional layout design method using the automatic placement/wiring tool. A description will be given of the conventional layout design method with reference to FIG. 1.
As shown in FIG. 1, the net list which describes the circuit information of a layout of a semiconductor integrated circuit to be created is read from the database at step S21. Next, a floor plan, such as creation of design size, is created at step S22.
The IO cells, the macro cells, and the standard cells are arranged at the desired locations on the floor plan (created at step S22) according to the cell information read from the macro-cell library, the standard-cell library, etc. at step S23.
After the step S23 is performed, the wiring of power supply lines which supply the source power to these cells is performed at step S24. At the step S24, the connection of the power supply lines with the macro cell and the standard cell is also performed.
After the wiring of the power supply lines is completed, the wiring of signal lines is performed at step S25.
After the wiring of the signal lines is completed, the post-processing, such as the removal of the DRC error, the data format conversion, etc. is performed at step S26. When the post-processing is completed, the semiconductor integrated circuit is created.
Moreover, the restrictions which are needed at each step can be inputted by the user each time. The structure information of the IO cells, the macro cells and the standard cells, used at the step S23, is beforehand prepared in the database as a layout library, and the automatic placement/wiring tool carries out the cell arrangement of the step S23 by making reference to the structure information stored in the layout library.
Next, a description will be given of several layout libraries used by the conventional layout design method.
FIG. 2 shows a standard cell pattern (the left diagram) used by the conventional layout design method, and its equivalent circuit (the right diagram).
As shown in the left diagram of FIG. 2, the transistor is arranged near the center of the cell, and the transistor is usually provided with a power rail (indicated by METAL-1 (VDD)) and a ground rail (indicated by METAL-1 (GND)) which are used as the power supply lines for supplying the power to the transistor. The power rail and the ground rail are arranged at the upper and lower portions of the center of the cell.
Usually, the power rail and the ground rail are formed by the metal (indicated by METAL-1) of the lowest layer (LAYER-1), in order to supply the source power to the diffusion layer of the transistor. The functional cell of FIG. 2 is the inverter as a typical example of the standard cell. However, there are different functional cells, such as NAND, NOR, etc., than the inverter, which may be provided as the standard cell pattern. These functional cells have the respective electrical properties which are different from each other. These cells are called collectively the standard cells, and the database which stores the structure information of these functional cells is called the standard-cell library.
On the other hand, the cells which have complicated functions, such as the memory, are called the macro cells, and the database which stores the structure information of the macro cells is called the macro-cell library. Moreover, the database which stores the structure information of the IO cells is called the IO cell library. The kinds of the cells stored in these libraries can be specified by the designer (or the user), and there is no special definition which specifies the composition of these libraries.
The standard cells and the macro cells described above have the predetermined functions (the functional cells). On the other hand, there are filler cells which have no predetermined function, like the transistor, but are provided with the power rail and the ground rail on the layer-1, similar to the standard cells. The structure information of the filler cells is also included in the standard-cell library.
FIG. 3 shows a filler cell used by the conventional layout design method.
The filler cells are provided for the purposes of preventing the violation of the design rule created between the standard cells, and of obtaining the substrate potential. In the conventional layout design method, the filler cells are arranged between the standard cells in the standard-cell region.
FIG. 4 shows a conventional chip layout of a semiconductor integrated circuit.
The layout of FIG. 4 corresponds to the layout when the cell arrangement of the step S23 in the flowchart of FIG. 1 is performed. As shown in FIG. 4, the IO cells are arranged on the peripheral portion of the chip layout. There is the standard-cell region in which the standard cells are arranged inside the IO cells. The macro cells may be arranged in the vacant region of the chip layout. Moreover, inside the IO cells, there are the channel regions in which the standard-cell region and the wiring of the signal lines and the power supply lines by which the macro cells are not arranged are connected.
FIG. 5A and FIG. 5B show the arrangement of the power supply lines to the chip layout of FIG. 4. FIG. 5B is an enlarged view of the portion of the layout indicated by the letter “A” in FIG. 5A.
As described previously, in the conventional layout design method, the filler cells are arranged between the standard cells in the standard-cell region as shown in FIG. 5B.
In recent years, the demands for high-speed semiconductor integrated circuits with advanced features are increasing. With such demands, the microscopic process of the semiconductor integrated circuit manufacture tends to progress. Using improved techniques, the improvement in the performance of the semiconductor integrated circuit has been proposed by the manufacturers. A description will now be given of some improved techniques of conventional layout design methods.
In order to optimize the power supply efficiency, the area in which the circuit element is not formed is used as a power line wiring region. For example, Japanese Laid-Open Patent Application No. 9-199601 discloses a semiconductor integrated circuit having such structure.
The standard cell has the problem in that it requires the external region where the power supply line and the standard cell are mutually connected. In order to eliminate the problem, the standard cell is provided with an internal region for connecting the power supply line to the standard cell perpendicularly with the power supply line. For example, Japanese Laid-Open Patent Application No. 10-41393 discloses a standard cell having such structure.
There is the problem that common dimensions of respective macro cells must be used in order to form the power supply lines and grounding lines at the upper and lower edge portions. To resolve the problem, the portion acting as the via hall which provides electrical connection with the power supply metal, is provided in each of the respective standard cells. For example, Japanese Laid-Open Patent Application No. 10-144794 discloses a semiconductor integrated circuit having such structure of standard cells.
In order to eliminate the influences of the wiring of signal lines, the top of the standard cells is shielded with the upper-layer metal layer. For example, Japanese Laid-Open Patent Application No. 11-330434 discloses a semiconductor device having such structure of the upper-layer metal shielding.
In order to increase the capability of current supply in the semiconductor integrated circuit, the second metal layer is provided as the power rail of standard cells. For example, Japanese Laid-Open Patent Application No. 2001-506429 discloses such arrangement of power supply lines.
As the microscopic process of the semiconductor integrated circuit manufacture progresses, some problems arise and it is demanded to take into consideration the circuit design stage. A description will be given of some problems which arise with the development of the microscopic process of the semiconductor integrated circuit manufacture.
1. Wiring Cost
The multilevel metallization progresses with the development of the microscopic process of the semiconductor integrated circuit manufacture. FIG. 6A and FIG. 6B show the microscopic structure of a segment of the chip layout of FIG. 5A. FIG. 6A is a plan view of the microscopic structure of the segment, and FIG. 6B is a cross-sectional view of the microscopic structure of the segment taken along the line A–A′ indicated in FIG. 6A.
In the conventional design technique, the wiring of signal lines is performed after the wiring of power supply lines is performed on the chip layout. As shown in FIG. 6B, the metal-1 of the layer-1 and the metal-8 of the layer-8 in the power supply wiring are connected together by means of the vertically extending vias. If this is done, the metals of the intermediate layers of the layer-2 to the layer-7 are not used for the wiring of signal lines. The disadvantage of wiring cost and the redundant wiring will take place.
2. Power Supply Noise/Voltage Drop
The integration level of the transistors progresses with the development of the microscopic process of the semiconductor integrated circuit manufacture, which results in the problem of power supply noise due to the charging and discharging current at the time of simultaneous switching of the transistors. Moreover, in the microscopic process, the voltage drop (IR-DROP) in which the voltage supplied to the transistor becomes excessively low arises.
The voltage drop is greatly dependent on the resistance of power supply wiring, and the power supply width gives significant influence on the chip size. The optimization of the power supply wiring is one of the important issues in the semiconductor integrated circuit design. However, in the current circumstances, it is difficult to analyze the complicated structure of the power supply wiring, and it is difficult to set up the optimal power supply width.
3. Planarization and Occupancy Rate
In the semiconductor integrated circuit manufacture, the planarization processing is performed by CMP (chemical and mechanical polishing). Especially, in the interlayer dielectric process of copper and low dielectric material, the problem, such as dishing, becomes remarkable as shown in FIG. 7. FIG. 7 shows the cross-section of the chip layer when the interlayer dielectric process of copper and low dielectric material is performed.
To eliminate the problem, it is necessary to take measures of creating dummy metal or the like so as to provide the mask pattern with uniform planarization, because there are many elements resulting from the occupancy rate of metal.
4. Complication of Power Supply Structure
The multilevel metallization progresses increasingly, and the configuration of the power supply structure where the advantage of the multilevel metallization is used efficiently makes it possible that the wiring of power supply lines does not cause the power supply noise and voltage drop, etc. However, because of the complicated structure of the power supply wiring, it is difficult for the conventional technique to realize it, or the man-hour needed to realize it is significantly increased.
5. Microscopic Process
In the microscopic process of the semiconductor integrated circuit manufacture, the manufacture processes of the conventional technique become complicated, and large-scale processing is required. It takes great time to carry out the semiconductor integrated circuit manufacture.